VLSI Design and RTL Development Internship

Design digital circuits at the register-transfer level in Verilog and VHDL, and verify them with Cadence and Synopsys tools. Online and project-based, about 12 hours a week, 1 to 6 months, with a certificate and 3 AICTE-approved credits.

• Tools: Verilog, VHDL, Cadence, Synopsys
• Example project: Design and verify digital circuits at the RTL level
• You practise: Digital design fundamentals
• You practise: RTL coding in Verilog and VHDL
• You practise: Simulation and verification
• You practise: Synthesis basics
• Duration option: 1 Month (30 Days)
• Duration option: 6 Weeks (45 Days)
• Duration option: 2 Months (60 Days)
• Duration option: 3 Months (90 Days)
• Duration option: 4 Months (120 Days)
• Duration option: 6 Months (180 Days)